The present invention pertains to fabrication of integrated circuits and more particularly to methods and systems for analyzing the performance and manufacturability of integrated circuits.
Miniaturization and scaling of integrated circuits have resulted in two conflicting trends. On one hand, margins available in high-performance designs are shrinking, increasing the likelihood that inevitable variations during manufacturing will cause performance violations. On the other hand, both the amount of variation as a fraction of the feature sizes, and the sensitivity of the characteristics of transistors and interconnects to manufacturing variations is increasing. This makes it essential to model and simulate accurately and efficiently the impact of manufacturing variations on the performance of integrated circuits.
Manufacturing variations include intra-die variations, hereinafter referred to as “local mismatch”, and inter-die variations, hereinafter referred to as “global variations”. Such intra-die and global variations are random and systematic variations in the material composition, or in the processing steps that are used to fabricate the integrated circuits. Local mismatch, or intra-die variations, are differences in the electrical properties of circuit elements that affect components of the circuits that are fabricated on the same die. For example, two identically drawn transistors fabricated next to each other in any particular chip will still present different threshold voltage values. Global variations, or inter-die variations, affect integrated circuit devices by causing random differences in the electrical properties of circuit elements, such as transistors, resistors, capacitors, memory cells, wires, etc., that are fabricated on different chips from the same wafer, on different wafers, or on different batches of wafers. As circuits are designed assuming i) a given nominal value of the electrical properties of its elements and ii) that identically drawn elements behave exactly in the same way, both global variations and local mismatch affect the actual circuit performance and are essential to determine the yield of the product.
Local mismatch has not been adequately modeled in the past. Accurate matching of the electrical properties of active and passive elements is fundamental for functional and parametric performances of analog and mixed-signal integrated performance (IP) blocks, such as operational amplifiers (OPAMPs), digital to analog (D/A) and analog to digital (A/D) converters, phase locked loops (PLLs), etc. Achieving target functional and parametric yield of analog and mixed-signal components frequently represents a major bottleneck for the global time-to-volume performance of complex very large scale integrated (VLSI) systems.
Previous work in modeling and analysis of matching properties of electronic devices, such as that described in the paper entitled “Matching Properties of MOS Transistors”, Pelgrom M., Dunjnmayer, A., and Welbers A., IEEE Journal of Solid State Circuits, Vol SC-24, pp 1433–1440, October 1989, which paper is incorporated by reference in this detailed description as if fully set forth herein, aims at deriving a suitable model of intra-die metal oxide semiconductor field effect transistor (MOSFET) variance as a function of device size, layout distance and orientation. Although these models have become popular, their direct application in the context of electrical circuit simulation is difficult for two main reasons.
First, they model the matching properties of MOSFET “macro” characteristics, such as threshold voltage (VTh) saturation current (IDSAT) that are only indirectly related to the actual “lowlevel” parameters of most widely used compact SPICE (System Program for Integrated Circuits Emphasis) simulation models, such as BSIM3v3 (“MOSFET Modeling and BSIM User Guide”, Cheng, Y and Hu, C., Kluwer Academic Publishers, Boston, 1999, incorporated by reference as if fully set forth herein) or MOS9 (“Compact Modeling for Analogue Circuit Simulation”, Veighe, R., et al., IEDM Tech. Digest, pp. 485488, 1993, incorporated by reference as if fully set forth herein). Therefore, a nontrivial inverse modeling process must be applied to extract the proper covariance structure of lowlevel SPICE model parameters corresponding to the available matching characterization data for these macro parameters.
Second, applying a device level mismatch model to the statistical simulation of electronic circuits requires the assumption that every matched device is described by a different set of low-level device parameters, each associated with a corresponding random variable (RV) (“Statistical Modeling of Device Mismatch for Analog Integrated Circuits”, Michael, C. and Ismail, M., IEEE Journal of Solid-State Circuits, Vol 27, No 2, February 1992; “Applying a Submicron Mismatch Model to Practical IC Design”, Guardiani, C. et al., IEEE CICC Conference, May 1994; “Hierarchical Statistical Circuit Characterization of Mixed-Signal Circuits using Behavioral Modeling”, Felt et al., IEEE-ACM International Conference on Computer Aided Design, San Jose, Calif., November 1996, all of which are incorporated by reference as if fully set forth herein).
The variance of the relevant circuit performance parameters can then be estimated via MonteCarlo analysis. This process requires the generation of a sequence of correlated vectors of random numbers, and the evaluation of the circuit performance corresponding to each random vector instance either by directly using SPICE or via RSM macro-modeling. The dimensionality of the corresponding RV space can be very large when the simultaneous variation of all matched n-tuples of devices is considered.
The problem associated with the large dimensionality of the mismatch simulation task has not yet been properly addressed. The σ-space approach of Michael and Ismail (cited above), which can be proven to be equivalent to the Choleski factorization technique used by Felt et al. (cited above), requires       [          [                        ∑                      i            =            1                    nd                ⁢                              (                                          N                ⁡                                  (                                      m                    j                                    )                                            -              1                        )                    ⁢          X          ⁢                                          ⁢                      N            ⁡                          (                              p                j                            )                                          ]        ]    ⁢          ⁢            ∑              j        =        1            nd        ⁢                  (                              N            ⁡                          (                              m                j                            )                                -          1                )            ⁢      X      ⁢                          ⁢              N        ⁡                  (                      p            j                    )                    different RVs, where, N(mj) is the number of matched devices of type j, N(pj) is the number of independent process factors used in the model of the jth device type, and nd is the number of different devices in the circuit.
The empirical approach of Guardiani et al. (cited above), has an even greater complexity, and can be only applied to very simple circuits. Conti (“Parametric Yield Formulation of MOS ICs affected by mismatch effect”, Conti, M., IEEE Transactions on Computer Aided Design, vol 18, pp. 582–596, May 1999, incorporated by reference as if fully set forth herein) proposed a method based on the experimental characterization of a parametrized auto-correlation function for the relevant process parameters described as spatial stochastic processes. The autocorrelation function is then used to derive a symbolic formula for the system covariance matrix as a function of the layout parameters. Therefore, the complexity of this methodology is also proportional to the same number of variables as the σ-space approach, however this technique is compatible with the statistical simulation methodology described herein, and can be used to replace the approach of deriving the component correlation matrix using a mismatch model.